//*****************************************************************************************/
// FILE NAME: eMIOS_OPS.c                                                                 */ 
// DESCRIPTION:                                                                           */ 
// This file contains functions for the MPC5554 to Initialize the eMIOS Engine            */ 
// 24 Unified Channels Available-channels 10-15 for eQADC Triggering                      */ 
//                                                                                        */ 
//========================================================================================*/ 
// REV      AUTHOR        DATE          DESCRIPTION OF CHANGE                             */ 
// ---      -----------   ----------    ---------------------                             */ 
// 3.0      J. Zeeff      1/Oct/11      Add Timer for OS and MPC5534 		          */ 
// 3.0      P. Schlein    3/Sep/11      Add Timer for Engine Control Events               */ 
// 2.0      P. Schlein    27/July/11    Include Trigger Channels 10 and 11 for eQADC      */ 
// 1.0      P. Schlein    27/July/10    Initial version                                   */ 
//*****************************************************************************************/ 
#include "config.h"
#include "cpu.h"
#include "system.h"
#include "eMIOS_OPS.h"
    
//*****************************************************************************************/ 
// FUNCTION     :  init_eMIOS                                                             */ 
// PURPOSE      :   Initialize 2 eMIOS Unified Channels for eQADC Triggering              */ 
//                  Note:  Ch(10) 100 samples/sec and Ch(11) at 1/sec                     */ 
//                  Also, Initializes CH[09] as a Timer                                   */ 
// INPUT NOTES  :                                                                         */ 
// RETURN NOTES :                                                                         */ 
// WARNING      : For testing, set output pads in SIU_OPS.  Nomal Ops use SIU_ETISR       */ 
//*****************************************************************************************/ 

void init_eMIOS(void)
{
    
//  First, configure the eMIOS for xxx mhz/250 internal clock with Module Config Reg        
//  see RM 17.3.1.1, 17-8, pg 628                                                          

EMIOS.MCR.B.GPRE = 249;    // Prescalar Divisor-NOTE yields 250 divisor              
EMIOS.MCR.B.ETB = 0;       // Disble external timebase, may use Chl 23 with STAC     
EMIOS.MCR.B.GPREN = 1;     // Enable eMIOS clock                                     
EMIOS.MCR.B.GTBE = 1;      // Enable global timebase                                 
EMIOS.MCR.B.FRZ = 0;       // Disable stopping channels in debug                     
 
//  Second, configure Ch(10) to FAST trigger eQADC CFIFO Ch(0) with OPWFM                  
//  set for 100 triggers/second, 10% duty cycle                                            
//  OPWFM-see RM 17.4.4.4.12, 17-39, pg 659; CCR-see RM 17.3.1.7, 17-13, pg 633,           
//  Initialization- see RM 17.5.1, 17-61, pg 682,  Note:  Resets in GPIO Mode              

EMIOS.CH[10].CCR.B.FEN = 0x00;     // Disable Interrupt Request                              
EMIOS.CH[10].CADR.R = (int32_t)((CPU_CLOCK / 100000) * .9);   // Leading edge when counter bus =1188                    
EMIOS.CH[10].CBDR.R = CPU_CLOCK / 100000;  // Trailing edge when counter bus =1320                   
EMIOS.CH[10].CCR.B.BSL = 0x03;     // Use internal counter                                   
EMIOS.CH[10].CCR.B.UCPRE = 0x3;    // Further Divide by 4 with internal channel prescaler    
EMIOS.CH[10].CCR.B.UCPREN = 1;     // Enable internal channel prescaler                      
EMIOS.CH[10].CCR.B.EDPOL = 1;      // Polarity-leading edge sets output, trailing clears     
EMIOS.CH[10].CCR.B.MODE = 0x18;    // Set OPWFM mode                                         
 
//  Third, configure Ch(11) to SLOW trigger eQADC CFIFO Ch(1) with OPWFM                   
//  set for 1 trigger/second, 10% duty cycle                                               
//  OPWFM-see RM 17.4.4.4.12, 17-39, pg 659; CCR-see RM 17.3.1.7, 17-13, pg 633            
//  Initialization- see RM 17.5.1, 17-61, pg 682,  Note:  Resets in GPIO Mode              

EMIOS.CH[11].CCR.B.FEN = 0x00;     // Disable Interrupt Request                              
EMIOS.CH[11].CADR.R = (int32_t)((CPU_CLOCK / 1000) * .9);     // Leading edge    
EMIOS.CH[11].CBDR.R = CPU_CLOCK / 1000;     // Trailing edge        
EMIOS.CH[11].CCR.B.BSL = 0x03;     // Use internal counter                                   
EMIOS.CH[11].CCR.B.UCPRE = 0x3;    // Further prescaling with internal channel prescaler     
EMIOS.CH[11].CCR.B.UCPREN = 1;     // Enable internal channel prescaler                      
EMIOS.CH[11].CCR.B.EDPOL = 1;      // Polarity-leading edge sets output, trailing clears     
EMIOS.CH[11].CCR.B.MODE = 0x18;    // Set OPWFM mode                                         
    
//  Fourth, configure a free running timer for general purpose and OS use               
//  Note:  with Prescalars set to 249 (249+1) and 3 (4), Counter runs at 132,000/sec       
//  MC mode-see RM 17.4.4.4.11, 17-38, pg 658; CCR-see RM 17.3.1.7, 17-13, pg 633          
//  CSR-see RM 17.3.1.8, 17-21, pg 641                                                     
//  Initialization- see RM 17.5.1, 17-61, pg 682,  Note:  Resets in GPIO Mode              
//  Final result - SYS_CLOCK / 1000000

EMIOS.CH[MSEC_EMIOS_CHANNEL].CCR.B.MODE = 0x01;    // Set GPIO Mode to Reset CNTR                             
EMIOS.CH[MSEC_EMIOS_CHANNEL].CCR.B.FEN = 0x00;     // Disable Interrupt Request                               
EMIOS.CH[MSEC_EMIOS_CHANNEL].CADR.R = 0xffffff;    // run free - no modulus
EMIOS.CH[MSEC_EMIOS_CHANNEL].CCR.B.BSL = 0x03;     // Use internal counter                                    
EMIOS.CH[MSEC_EMIOS_CHANNEL].CCR.B.UCPRE = 0x3;    // Further 1/4x with internal channel prescaler      
EMIOS.CH[MSEC_EMIOS_CHANNEL].CCR.B.UCPREN = 1;     // Enable internal channel prescaler                       
    
#ifdef MPC5554
        EMIOS.CH[MSEC_EMIOS_CHANNEL].CCR.B.MODE = 0x10; // Set MC up counter mode                                  
#endif   
 
#ifdef MPC5634
        EMIOS.CH[MSEC_EMIOS_CHANNEL].CCR.B.MODE = 0x50; // Set MC up buffer mode                                   
#endif  

// Example: Configure Channel 5 - OPWM, BUS A, EDPOL=1, PRE=0 
//EMIOS.CH[5].CCR.R = 0x020000E0;
//EMIOS.CH[5].CADR.R = 0x2800; //0x2800;
//EMIOS.CH[5].CBDR.R = 0x5000; //0x5000;  //Set up fo 16ms rising edge to rising edge
// OBE=ON, IBE=ON, Primary mode
//SIU.PCR[eMIOS5_PIN].R = 0x0600;

#ifdef MPC5634
// enable STM counter in case we want to use it for measuring code execution speed
STM.CR.R = 0x00003;     // enable, no divisor, stop with debug
#endif


} // init_eMIOS()
